|
NISCAIR ONLINE PERIODICALS REPOSITORY (NOPR) >
NISCAIR PUBLICATIONS >
Research Journals >
Journal of Scientific and Industrial Research (JSIR) >
JSIR Vol.69 [2010] >
JSIR Vol.69(01) [January 2010] >
| Title: | A novel logarithmic prefix adder with minimized power delay product |
| Authors: | Ramanathan, P
Vanathi, P T |
| Keywords: | Complementary metal oxide semiconductor (CMOS)
Dot operator
Parallel prefix adder (PPA)
Semi-dot operator |
| Issue Date: | Jan-2010 |
| Publisher: | CSIR |
| Abstract: | Parallel prefix addition is a technique for speeding up binary addition. Classical parallel prefix adder structures developed so far are optimized for logic depth, area, fan-out and interconnect count of logic circuits. Due to continuing integrating intensity and growing needs of portable devices, low-power and high-performance designs are of prime importance. A new technique, proposed for performing parallel prefix addition, has least power delay product in comparison with its peer prefix adder structures. Tanner EDA tool was used for simulation in TSMC 180 nm technology. |
| Page(s): | 17-20 |
| ISSN: | 0975-1084 (Online); 0022-4456 (Print) |
| Source: | JSIR Vol.69(01) [January 2010]
|
|
