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dc.contributor.authorJames, Britto Pari-
dc.contributor.authorDhandapani, Vaithiyanathan-
dc.contributor.authorMariammal, Karuthapandian-
dc.identifier.issn0975-1017 (Online); 0971-4588 (Print)-
dc.description.abstractFilter design in signal processing field plays a vital role in achieving low power dissipation, which is essential for portable gadgets. This paper proposes an effective flexible FIR filter structure, which is adaptive and utilizes multiply–accumulate (MAC) core. Most common algorithm for filter coefficient optimization includes least mean square (LMS) and recursive least square (RLS). Though the performance of the recursive least square (RLS) algorithm is superior as compared to the least mean square (LMS); because of higher arithmetic complexity in design, it has not been preferred for real time applications. The fundamental filter has used a LMS based tapped delay line filter, which is practically a feasible choice for adaptive filtering algorithm in order to attain lesser computation. In the proposed work, the adjustable coefficient filters using an optimized LMS approach has been implemented for the utilization of determining the unexplored system. The filter tap considered here is a 32-tap and its analysis and synthesis has been carried out using hardware description language (HDL) programming and synthesized in field programmable gate array (FPGA) devices. The placement and post routing design has offered good performance in terms of utilized resources. The implemented filter architecture requires 80% reduction in resources and has enhanced the clock frequency by about five times when examined with the reported architecture.en_US
dc.publisherNISCAIR-CSIR, Indiaen_US
dc.rights CC Attribution-Noncommercial-No Derivative Works 2.5 Indiaen_US
dc.sourceIJEMS Vol.27(4) [August 2020]en_US
dc.subjectMemory optimisationen_US
dc.subjectAdaptive filteren_US
dc.titleAn optimized MAC based architecture for adaptive digital filteren_US
Appears in Collections:IJEMS Vol.27(4) [August 2020]

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