Please use this identifier to cite or link to this item: http://nopr.niscair.res.in/handle/123456789/55676
Title: An optimized MAC based architecture for adaptive digital filter
Authors: James, Britto Pari
Dhandapani, Vaithiyanathan
Mariammal, Karuthapandian
Keywords: Memory optimisation;Adaptive filter;LMS;FIR;MAC;FPGA
Issue Date: Aug-2020
Publisher: NISCAIR-CSIR, India
Abstract: Filter design in signal processing field plays a vital role in achieving low power dissipation, which is essential for portable gadgets. This paper proposes an effective flexible FIR filter structure, which is adaptive and utilizes multiply–accumulate (MAC) core. Most common algorithm for filter coefficient optimization includes least mean square (LMS) and recursive least square (RLS). Though the performance of the recursive least square (RLS) algorithm is superior as compared to the least mean square (LMS); because of higher arithmetic complexity in design, it has not been preferred for real time applications. The fundamental filter has used a LMS based tapped delay line filter, which is practically a feasible choice for adaptive filtering algorithm in order to attain lesser computation. In the proposed work, the adjustable coefficient filters using an optimized LMS approach has been implemented for the utilization of determining the unexplored system. The filter tap considered here is a 32-tap and its analysis and synthesis has been carried out using hardware description language (HDL) programming and synthesized in field programmable gate array (FPGA) devices. The placement and post routing design has offered good performance in terms of utilized resources. The implemented filter architecture requires 80% reduction in resources and has enhanced the clock frequency by about five times when examined with the reported architecture.
Page(s): 906-915
URI: http://nopr.niscair.res.in/handle/123456789/55676
ISSN: 0975-1017 (Online); 0971-4588 (Print)
Appears in Collections:IJEMS Vol.27(4) [August 2020]

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