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dc.contributor.authorAdhikari, Manoj Singh-
dc.contributor.authorPatel, Raju-
dc.contributor.authorTripathi, Suman Lata-
dc.contributor.authorSingh, Yashvir-
dc.identifier.issn0975-0959 (Online); 0301-1208 (Print)-
dc.description.abstractIn this paper, the concept of integration of a high voltage trench MOSFET (HVT MOSFET) and low voltage trench MOSFET (LVT MOSFET) is proposed. Insulator (Dielectric) isolation technique is used for the implementation of HVT and LVT MOSFETs on Silicon-on-Insulator (SOI) layer side by side. The HVT MOSFET consists of two gates which are placed in separate trenches in the drift region. The proposed structure minimizes ON-resistance (Ron) along with increased breakdown voltage (Vbr) due to reduced electric field, creation of dual channels, and folding of drift region in vertical direction. In HVT MOSFET, the drain current (ID) increases leading to enhanced trans conductance (gm) by simultaneous conduction of channels which improves the cut-off frequency (ft) and maximum oscillation frequency (fmax). On the other side, LVT MOSFET consists of a gate placed within a SiO2 trench to create two channels on either side of gate. The parallel conduction of two channels provides enhancement in ID, gm, fmax and ft. The performance analysis of HVT MOSFET and LVT MOSFET is carried out using 2D simulation in the device simulator (ATLAS).en_US
dc.publisherNISCAIR-CSIR, Indiaen_US
dc.rights CC Attribution-Noncommercial-No Derivative Works 2.5 Indiaen_US
dc.sourceIJPAP Vol.58(09) [September 2020]en_US
dc.subjectBreakdown voltageen_US
dc.subjectTrans conductanceen_US
dc.titleDesign of SOI MOSFETs for Analog/RF Circuitsen_US
Appears in Collections:IJPAP Vol.58(09) [September 2020]

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