Please use this identifier to cite or link to this item: http://nopr.niscair.res.in/handle/123456789/53589
Title: Low Latency Prefix Accumulation Driven Compound MAC Unit for Efficient FIR Filter Implementation
Authors: Hemantha, G Reddy
Varadarajan, S
Giriprasad, M N
Keywords: Multiply Accumulate (MAC) unit;Distributed arithmetic;FIR filter;Compound adder
Issue Date: Feb-2020
Publisher: NISCAIR-CSIR, India
Abstract: This article presents hierarchical single compound adder-based MAC with assertion based error correction for speculation variations in the prefix addition for FIR filter design. The VLSI implementation of approximation in prefix adder results show a significant delay and complexity reductions, all this at the cost of latency measures when speculation fails during carry propagation, which is the main reason preventing the use of speculation in parallel-prefix adders in DSP applications. The speculative adder which is based on Han Carlson parallel prefix adder structure accomplishes better reduction in latency. Introducing a structured and efficient shift-add technique and explore latency reduction by incorporating approximation in addition. The improvements made in terms of reduction in latency and merits in performance by the proposed MAC unit are showed through the synthesis done by FPGA hardware. Results show that proposed method outpaces both formerly projected MAC designs using multiplication methods for attaining high speed.
Page(s): 135–138
URI: http://nopr.niscair.res.in/handle/123456789/53589
ISSN: 0975-1084 (Online); 0022-4456 (Print)
Appears in Collections:JSIR Vol.79(02) [February 2020]

Files in This Item:
File Description SizeFormat 
JSIR 79(2) 135-138.pdf274.18 kBAdobe PDFView/Open


Items in NOPR are protected by copyright, with all rights reserved, unless otherwise indicated.