Please use this identifier to cite or link to this item: http://nopr.niscair.res.in/handle/123456789/5135
Title: Comparison of pipelined IEEE-754 standard floating point adder with unpipelined adder
Authors: Khare, Kavita
Singh, R P
Khare, Nilay
Keywords: Floating point adder
IEEE floating point standard
Latency
Model-Sim
Pipelining
VHDL
Xilinx ISE 5.2i
Issue Date: May-2005
Publisher: CSIR
Abstract: Many Digital Signal Processing (DSP) algorithms use floating-point arithmetic, which requires millions of calculations per second to be performed. For such stringent requirements, design of fast, precise and efficient circuits is the goal of every VLSI designer. This paper presents a comparison of pipelined floating-point adder complaint with IEEE 754 format with an unpipelined adder also complaint with IEEE 754 format. It describes the IEEE floating-point standard 754. A pipelined floating point adder based on IEEE 754 format is developed and the design is compared with that of an unpipelined floating point adder and a rigorous analysis is done for speed, area, and power considerations. The functional partitioning of the adder into four distinct stages operates simultaneously for different serial input data stream. It not only increases the speed but also is energy efficient. All these improvements are at the cost of slight increase in the chip area. The basic methodology and approach used for VHDL (Very Large Scale Integration Hardware Descriptive Language) implementation of the floating-point adder are also described. Detailed synthesis report operated upon Xilinx ISE 5.2i software and Modelsim is given. The hardware design is implemented on Spartan IIE FPGA chip.
Description: 354-357
URI: http://hdl.handle.net/123456789/5135
ISSN: 0975-1084 (Online); 0022-4456 (Print)
Appears in Collections:JSIR Vol.64(05) [May 2005]

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