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|Title:||Comparison of pipelined IEEE-754 standard floating point multiplier with unpipelined multiplier|
Singh, R P
|Keywords:||Floating point adder;IEEE floating point standard;Latency;Model-Sim;VHDL;Xilinx ISE 5.2i|
|Abstract:||The IEEE-754 standard floating point multiplier that provides highly precise computations to achieve high throughput and low area on the IC have been improved by insertion of pipelining technique. Floating point multiplier-using pipelining has been simulated, analyzed and its superiority over traditional designs is discussed. To achieve pipelining, one must subdivide the input process into sequence subtasks, each of which can be executed by specialized hardware stage that operates concurrently with other stages in the pipeline without the need of extra computing units. Detailed synthesis and simulation report operated upon Xilinx ISE 5.2i and Modelsim software is given. Hardware design is implemented on Virtex FPGA chips.|
|ISSN:||0975-1084 (Online); 0022-4456 (Print)|
|Appears in Collections:||JSIR Vol.65(11) [November 2006]|
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