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dc.contributor.authorSharma, Suman-
dc.contributor.authorShukla, Rajni-
dc.contributor.authorTripathy, M R-
dc.identifier.issn0975-0959 (Online); 0301-1208 (Print)-
dc.description.abstractThe present study provides the comprehensive appraisal of analog/RF performance of dielectric engineered gate all around junctionless MOSFET by the assimilation of gate material engineered along with ZrTiO4 as high-k gate dielectric. The radical reductions in impact of positive and negative interface traps have been reported, which augment the device reliability. The cylindrical geometry of the MOSFET accounts for the self heating effect in the device, which accelerates the practice of hot carrier effect and diffusion of H, conscientious for negative bias temperature instability (NBTI) effect in P-MOSFET and PBTI effect in the N-MOSFET. The proposed design has been studied by taking SiO2, and orthorhombic ZrTiO4 symmetric gate stack to improve the reliability of the device. The electrical characteristics like Id-Vg, electric field, centre potential, transconductance and frequency have been measured using the ATLAS 3D simulator. Orthorhombic ZrTiO4 with dielectric constant 45.9 shows the enhanced performance of the device. The interface trap charge concentration of 1×1011 cm-2 (positive and negative both) for ZrTiO4 have been compared with the device devoid of gate stack which provides the knowledge about the RF and analog performance of the MOSFET.en_US
dc.publisherNISCAIR-CSIR, Indiaen_US
dc.rights CC Attribution-Noncommercial-No Derivative Works 2.5 Indiaen_US
dc.sourceIJPAP Vol.56(11) [November 2018]en_US
dc.subjectHigh-k gate dielectricen_US
dc.subjectInterface trap chargesen_US
dc.titleAnalog/RF performance and effect of interface trap charges in dielectric engineered gate all around junctionless MOSFET with ZrTiO4 as gate dielectricen_US
Appears in Collections:IJPAP Vol.56(11) [November 2018]

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