Please use this identifier to cite or link to this item: http://nopr.niscair.res.in/handle/123456789/44946
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dc.contributor.authorKuppuswamy, C L-
dc.contributor.authorRaghavendiran, T A-
dc.date.accessioned2018-09-04T09:36:32Z-
dc.date.available2018-09-04T09:36:32Z-
dc.date.issued2018-09-
dc.identifier.issn0975-1084 (Online); 0022-4456 (Print)-
dc.identifier.urihttp://nopr.niscair.res.in/handle/123456789/44946-
dc.description504-509en_US
dc.description.abstractThis work proposes FPGA implementation of Carrier Disposition PWM for closed loop seven level diode clamped multilevel inverter in speed control of induction motor. VLSI architecture for carrier Disposition have been introduced through which PWM signals are fed to the neutral point seven level diode clamped multilevel using which the speed of the induction motor is controlled. This proposed VLSI architecture makes the power circuit to work better with reduced stresses across the switches and a very low voltage and current total harmonic distortion (THD). The output voltages, currents, torque & speed characteristics for seven level neutral point diode clamped multilevel inverter for AC drive was studied. It has observed the proposed scheme introduces less distortion and harmonics. The results were validated using real time THD meters.en_US
dc.language.isoen_USen_US
dc.publisherNISCAIR-CSIR, Indiaen_US
dc.rights CC Attribution-Noncommercial-No Derivative Works 2.5 Indiaen_US
dc.sourceJSIR Vol.77(09) [September 2018]en_US
dc.subjectVLSI Architecture for Phase Disposition Shifted PWMen_US
dc.subjectDiode Clamped Multilevel Inverteren_US
dc.subjectTotal Harmonic Distortionen_US
dc.titleFPGA Implementation of Carrier Disposition PWM for Closed Loop Seven Level Diode Clamped Multilevel Inverter in Speed Control of Induction Motoren_US
dc.typeArticleen_US
Appears in Collections:JSIR Vol.77(09) [September 2018]

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