Please use this identifier to cite or link to this item: http://nopr.niscair.res.in/handle/123456789/44946
Title: FPGA Implementation of Carrier Disposition PWM for Closed Loop Seven Level Diode Clamped Multilevel Inverter in Speed Control of Induction Motor
Authors: Kuppuswamy, C L
Raghavendiran, T A
Keywords: VLSI Architecture for Phase Disposition Shifted PWM;Diode Clamped Multilevel Inverter;Total Harmonic Distortion
Issue Date: Sep-2018
Publisher: NISCAIR-CSIR, India
Abstract: This work proposes FPGA implementation of Carrier Disposition PWM for closed loop seven level diode clamped multilevel inverter in speed control of induction motor. VLSI architecture for carrier Disposition have been introduced through which PWM signals are fed to the neutral point seven level diode clamped multilevel using which the speed of the induction motor is controlled. This proposed VLSI architecture makes the power circuit to work better with reduced stresses across the switches and a very low voltage and current total harmonic distortion (THD). The output voltages, currents, torque & speed characteristics for seven level neutral point diode clamped multilevel inverter for AC drive was studied. It has observed the proposed scheme introduces less distortion and harmonics. The results were validated using real time THD meters.
Page(s): 504-509
URI: http://nopr.niscair.res.in/handle/123456789/44946
ISSN: 0975-1084 (Online); 0022-4456 (Print)
Appears in Collections:JSIR Vol.77(09) [September 2018]

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