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Journal of Scientific and Industrial Research (JSIR) >
JSIR Vol.68 [2009] >
JSIR Vol.68(05) [May 2009] >
| Title: | 24 Bit seismic processor for analyzing extra large dynamic range signals for early warnings |
| Authors: | Kumar, Satish
Sharma, B K
Sharma, Parkhi
Shamshi, M A |
| Keywords: | 24 Bit seismic processor
Digital seismograph
Early warning
Earthquake
Seismic Alert System |
| Issue Date: | May-2009 |
| Publisher: | CSIR |
| Abstract: | Modified design is presented of existing 24 bit seismic data recorder comprising PC –architecture using PCI bus, ISA bus,
and PC 104 bus in a single module to develop a flexible measurement set up. Paper elaborates use of building blocks [Disk on
chip (DoC), GPS based timing unit, signal-processing module, and efficient software packages] worked out in visual C++ to
develop compact sized instrument for quick decision-making with minimum error detection of true events. Paper describes
Ethernet connectivity use for data downloading in a laptop without interruption of event data acquisition. Software packages
for conversion of recorded data into SUDS and SEISAN formats have been realized and incorporated. |
| Page(s): | 372-378 |
| ISSN: | 0022-4456 |
| Source: | JSIR Vol.68(05) [May 2009]
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