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JSIR Vol.68 [2009] >
JSIR Vol.68(02) [February 2009] >
| Title: | Design and VLSI architecture of non-polynomial based low |
| Authors: | Arun, C
Rajamani, V |
| Keywords: | Add compare select (ACS)
Branch metric unit (BMU)
Free distance
Low bit error rate
Non-polynomial approach
Trace back unit (TBU)
Viterbi algorithm |
| Issue Date: | Feb-2009 |
| Publisher: | CSIR |
| Abstract: | This paper presents implementation of a new non-polynomial approach to design a high throughput with reduced bit error
probability Viterbi decoder. Increase in dfree has been achieved by proposed non-polynomial convolutional coding method. A
decoder system (code rate k/n=1/6, constrain length K=4) has been implemented on Xilinx VERTEX-E. Performance of
Viterbi decoder with proposed method has been improved from 27% to 75%. High speed (60.299 Mbps) and low bit error rate
(BER) are achieved for Viterbi decoder. Proposed Viterbi decoder provides satisfactory probability of error (Ph) performance
and high operating speed under conditions including AWGN, co-channel interference and adjacent channel interference
environments. |
| Page(s): | 97-106 |
| ISSN: | 0019-5189 |
| Source: | JSIR Vol.68(02) [February 2009]
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