Please use this identifier to cite or link to this item:
Title: Study and comparison of CMOS layouts for applications in analog circuits
Authors: López, Francisco
Estrada, Johan
Linares, Monico
Zúñiga, Carlos
Soto, Blanca
Keywords: Integrated Circuit (IC);Layout;Operational Amplifier;Serpentine
Issue Date: Apr-2012
Publisher: NISCAIR-CSIR, India
Abstract: This study presents different layouts techniques (serpentine, concentric, interdigitated) applied to a differential amplifier designed in commercial technology CMOS (0.6 μm). It was observed that serpentine technique improves by 6 to 7 electrical parameters, where area was reduced (64%) and power consumption diminishes until a 57% with respect to conventional technique. Thus designer can optimally use different abstraction levels during integrated circuits (IC) design, by applying the best layout technique towards efficient systems.
Page(s): 257-261
ISSN: 0975-1084 (Online); 0022-4456 (Print)
Appears in Collections:JSIR Vol.71(04) [April 2012]

Files in This Item:
File Description SizeFormat 
JSIR 71(4) 257-261.pdf477.75 kBAdobe PDFView/Open

Items in NOPR are protected by copyright, with all rights reserved, unless otherwise indicated.